Interrupts are a commonly used mechanism for peripheral devices to request the service of a central processing unit (CPU). For example, a parallel port connected to a printer can generate an interrupt to the CPU requesting that the CPU transmit additional characters to the printer. In this way, the CPU is able to perform other tasks until the printer requires service.
FIG. 1A illustrates an exemplary interrupt-driven computer system 100. There is shown a CPU 102, an interrupt controller 104, an interrupt router 106, and a host/PCI bridge 108, each of which are connected to a host bus 110. One or more peripheral component interface (PCI) devices 112A-112N are connected to a PCI bus 114. In addition, the host/PCI bridge 108 and the interrupt router 106 are connected to the PCI bus 114.
A PCI device 112 can be either an add-in board inserted into a PCI slot or a component embedded on the PCI bus 114. Four interrupt pins are associated with each PCI device 112 and are herein referred to as pin A, pin B, pin C, and pin D. Pin A is typically associated with the INTA# interrupt signal, pin B is associated with the INTB# interrupt signal, pin C is associated with the INTC# interrupt signal and pin D is associated with the INTD# interrupt signal. Typically, single-function PCI devices utilize pin A and multi-function PCI devices can utilize more than one interrupt pin.
The interrupt pins associated with each PCI device 112 can be connected to the system board traces or interrupt signals in a variety of ways. One such way is shown in FIG. 1B where the interrupt signals are shared between the PCI devices. The interrupt signals are shared in order to efficiently balance the load on each interrupt signal.
There is shown three PCI devices, 112A, 112B, 112C, where the interrupt traces or signals are shared between the three PCI devices, 112A-112C. Interrupt trace or signal INTA# is tied to interrupt pin B of PCI device.sub.1 112A, interrupt pin C of PCI device.sub.2 112B, and interrupt pin A of PCI device.sub.3 112C. Interrupt signal INTB# is tied to interrupt pin C of PCI device.sub.1 112A, interrupt pin A of PCI device.sub.2 112B, and interrupt pin B of PCI device.sub.3 112C. Likewise, interrupt signal INTC# is tied to interrupt pin A of PCI device.sub.1 112A, interrupt pin B of PCI device.sub.2 112B, and interrupt pin C of PCI device.sub.3 112C. All of the D pins are tied to the INTD# signal.
Each of the interrupt signals, INTA#-INTD#, is hardwired to a separate input of an interrupt router 106. The interrupt router 106 is used to assign each interrupt signal, INTA#-INTD#, to a specific interrupt request line, IRQ.sub.1 -IRQ.sub.L. The interrupt controller 104 receives the interrupt request lines, IRQ.sub.1 -IRQ.sub.L, and in response asserts a corresponding interrupt request 116 to the CPU 102.
A drawback with the interrupt sharing scheme described above is that some PCI devices are not capable of sharing interrupt signals with other PCI devices. For example, when a small computer system interface (SCSI) controller designed by one manufacturer is sharing an interrupt signal with a network interface card designed by a different manufacturer, a system failure sometimes occurs. At times this is attributable to problems with the device drivers associated with a particular PCI device. In this case, the PCI devices are moved around in the various PCI slots in order to prevent the troublesome devices from sharing the same interrupt signal. These failures and the manual intervention required to reconfigure the PCI devices impedes the overall performance of the computer system. Accordingly, there exists a need for a mechanism that can overcome this shortcoming.